Simplify I2C electrical validation and software protocol decoding

I2C Bus Overview:

In the early 1980s, Philips Semiconductor developed a simple 2-wire bidirectional bus for efficient control between ICs. This bus is called the Inter IC or I2C bus. All I2C bus compatible devices have an on-chip interface that allows them to communicate directly with each other over the I2C bus.

The I2C two-wire physical interface consists of a bidirectional serial clock (SCL) and data (SDA) lines. Each device that is connected to the bus is software addressable by a unique address and a simple master/slave relationship exists with the bus at all times. I2C is an 8-bit oriented, bidirectional serial data transfer that can be performed at 100 Kbits/s in standard mode, up to 400 Kbits/s in fast mode, up to 1 Mbits/s in fast plus mode, or up to 3.4Mbps in high speed mode. On-chip filtering rejects spikes on the bus data line to preserve data integrity.

Phillips Semiconductor (now NXP Semiconductors) has published electrical specifications and protocol specifications since 1982. The most recent I2C bus specification and user manual was published in 2007. By following the electrical and protocol specification in the I2C document, the Semiconductor design and manufacturing companies can ensure interoperability of integrated circuits using the I2C bus.

I2C Protocol Overview:

Typical data transfer between two ICs using the I2C interface is as follows:

All transactions start with the START condition and stop with the STOP condition on the I2C bus. These two conditions are controlled by the master IC. The typical I2C frame format has the following contents: START, address, read/write, data followed by ACK/NACK, and STOP condition at the end of the operation.

START: A condition in which a high-to-low transition of the SDA line occurs when SCL is held high. The is started by the master IC.

Address: the master sends the slave the 7 or 10 bit address of the slave device

Read/Write: The slave address is followed by this bit. A ZERO indicates a transmission (write) and a ‘ONE’ indicates a READ request.

Acknowledgment (ACK) and No Acknowledgment (NACK): This occurs after each byte. During this condition, the transmitter releases the SDA line during the acknowledgment clock pulse so that the receiver can pull the SDA line low, and the SDA line remains steady LOW during the HIGH period of this clock pulse.

When SDA remains HIGH during this ninth clock pulse, this is defined as the No Acknowledgment signal. The master can then generate a STOP condition to cancel the transfer or a repeated START condition to start a new transfer.

The data is an integer number of bytes read or written to the device.

STOP: A condition during SDA transitions from LOW to HIGH when SCL is held high, indicating the end of data transfer.

I2C electrical measurements:

For successful IC interoperation using the I2C bus, the physical layer signal electrical characteristics of the I2C SCL and SDA signals must be compatible. The timing between the master and slave devices must be within the electrical specifications defined in the NXP Semiconductor I2C specification.

Electrical Measurement Challenges:

During electrical validation of the I2C bus, test engineers must ensure that the I2C bus meets the electrical parameters of the I2C bus. The challenges faced during the electrical validation of the I2C bus are as follows:

• The test/design engineer must understand the behavior of the I2C protocol at the physical layer of the I2C bus.

• Measurements of electrical parameters must be performed in different protocol states (example; stop bit, acknowledgment bit, etc.)

• Reference level for each of the measurement changes depending on the rising or falling edge of the I2C signal transition

• Reference level is 30% or 70% compared to the commonly used reference level of 10% to 90% or 20% to 80%

• Validation is time consuming

In general, measuring I2C electrical measurements requires a very high level of expertise in I2C physical layer behavior, protocol layer, oscilloscope signal acquisition, and I2C electrical measurement procedures. Due to the complexity of I2C electrical measurements, the results can be error prone.

Simplifying I2C Electrical Measurements Using PGY-I2C Electrical Validation and Protocol Decoding Software:

PGY-I2C electrical validation and protocol decoding software provides electrical measurements and protocol decoding as specified in the I2C bus specification Rev 03, June 2007. Design and test engineers can now automatically perform accurate electrical measurements and and decode protocols in PGY-I2C software using data acquired by Tektronix DPO5000, DPO7000, DPO/DSA/MSO70000 series oscilloscopes to reduce development and test cycle.

PGY-I2C software runs inside Tektronix oscilloscopes. During the application execution operation, PGY-I2C sends commands to acquire SCL and SDA signals from the I2C bus. For accurate measurements, the recommended oscilloscope settings are:

• The signal is at least 5 to 6 six major vertical divisions on the oscilloscope screen with the appropriate volts per division

• Select the appropriate volts per division to display the signal with at least 5 or 6 main vertical divisions.

• Select a sample rate such that at least 8 to 10 samples are present on the rising or falling edge of the SCL and SDA signals.

• Set the recording duration so that at least two I2C frames are captured to take full advantage of I2C signals.

The application performs each of the I2C electrical measurements in all possible states of the I2C protocol and displays the minimum, maximum and average values. If the mean value is within the specified limit, the application displays ‘Pass’. But in case the mean value passes, but the minimum or maximum values ​​exceed the limits, the applications will show ‘passed*’ with an asterisk.

PGY-I2C performs all these measurements in an instant and addresses all the challenges of I2C electrical measurements, providing accurate and reliable measurements.

The ‘Detailed View’ in the Analyze panel provides protocol and measurement information for each I2C packet. This would help debug the I2C bus in a system. On a master-slave I2C bus, different ICs would communicate. There is potential for interoperability issues between ICs that use the I2C bus. This problem could be caused by the following reasons.

• Problems due to signal integrity on PCB

• EMI/EMC problems

• Non-strict compliance with the electrical characteristics of the I2C standard specification

The ‘Detailed View’ would help isolate interoperability issues by providing the physical layer waveform, electrical measurements for each I2C message/frame, and protocol decoding.

The detailed view contains the following information:

• Waveform graph of acquired data

• Protocol decoding in I2C packet/frame or I2C message format

• Electrical measurements for each I2C message or I2C packet/frame

• Selected I2C message or packet/frame waveform graph with decoded protocol data overlaid on waveform

• Utility functions such as cursors, cursor time readout, zoom, undo, fit-to-screen, and pan

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